Methods for filling a gap and related systems and devices

ABSTRACT

Methods and related systems for filling a gap feature comprised in a substrate are disclosed. The methods comprise a step of providing a substrate comprising one or more gap features into a reaction chamber. The one or more gap features comprise an upper part comprising an upper surface and a lower part comprising a lower surface. The methods further comprise a step of subjecting the substrate to a plasma treatment. Thus, the upper surface is inhibited while leaving the lower surface substantially unaffected. Then, the methods comprise a step of selectively depositing a silicon-containing material on the lower surface.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Provisional Patent Application Ser. No. 63/117,683 filed Nov. 24, 2020 titled METHODS FOR FILLING A GAP AND RELATED SYSTEMS AND DEVICES, the disclosure of which is hereby incorporated by reference in its entirety.

FIELD OF INVENTION

The present disclosure generally relates to methods and systems suitable for forming electronic devices. More particularly, the disclosure relates to methods and systems that can be used for depositing a material in gaps, trenches, and the like.

BACKGROUND OF THE DISCLOSURE

The scaling of semiconductor devices has led to significant improvements in speed and density of integrated circuits. However, with miniaturization of wiring pitch of large scale integration devices, void-free filling of high aspect ratio gaps or trenches (e.g. trenches having an aspect ratio of three or higher) becomes increasingly due to limitations of existing deposition processes. Therefore, there is a need for processes that efficiently fill high aspect ratio features, e.g. gaps such as trenches on semiconductor substrates, for example in the context of logic and/or memory devices. There is a particular need for processes that efficiently fill high aspect ratio features with silicon-containing materials such as silicon oxide that adequately withstand subsequent chemical mechanical polishing (CMP) steps and etching processes.

Any discussion, including discussion of problems and solutions, set forth in this section has been included in this disclosure solely for the purpose of providing a context for the present disclosure. Such discussion should not be taken as an admission that any or all of the information was known at the time the invention was made or otherwise constitutes prior art.

SUMMARY OF THE DISCLOSURE

Various embodiments of the present disclosure relate to gap filling methods, to structures and devices formed using such methods, and to apparatus for performing the methods and/or for forming the structure and/or devices. The ways in which various embodiments of the present disclosure address drawbacks of prior methods and systems are discussed in more detail below.

Described herein is a method for filling a gap feature on a substrate surface. The method comprises, in the order as given, a step of positioning a substrate on a substrate support in a reaction chamber. The substrate comprises one or more gap features. The one or more gap features comprise an upper part comprising an upper surface and a lower part comprising a lower surface. The method further comprises a step of subjecting the substrate to a plasma pre-treatment. The plasma treatment results in an inhibition of the upper surface while leaving the lower surface substantially unaffected. The method further comprises a step of selectively depositing a silicon-containing material on the lower surface. The step of depositing a silicon-containing material on the lower surface comprises a cyclical process. The cyclical process comprises a plurality of sub cycles. A sub cycle comprises, in the giving order: a step of exposing the substrate to a silicon precursor comprising an amine group and two or more silicon atoms. The substrate is particularly exposed to the silicon precursor in a silicon precursor pulse to form chemisorbed silicon precursor on the lower surface. A sub cycle further comprises a step of exposing the substrate to a post silicon precursor pulse plasma treatment, thus allowing one or more reactive species comprised in the plasma to react with the chemisorbed silicon precursor on the lower surface.

In some embodiments, the amine group is selected from NH₂, NHR^(i), and NR^(i)R^(ii), with at least one of R^(i) and R^(ii) being a C₁ to C₄ alkyl.

In some embodiments, the silicon precursor comprises a compound selected from the list consisting of an aminosilane, a silylamine, and a cyclosiloxane.

In some embodiments, the silicon precursor comprises an alkylaminosilane.

In some embodiments, the silicon precursor comprises a compound selected from SiR¹R³R⁴—SiR²R⁵R⁶, SiR¹R³R⁴—SiR⁵R⁶—SiR²R⁷R⁸, and SiR¹R³R⁴—SiR²R⁵—SiR⁶R⁷R⁸, wherein R¹ and R² are NR⁹R¹⁰, with R³, R⁴, R⁵, R⁶ R⁷, R⁸ R⁹, and R¹⁰ are independently selected from H and a C₁ to C₄ alkyl.

In some embodiments, the silicon precursor comprises a compound selected from R¹—SiH₂—SiH₃, R¹—SiH₂—SiH₂—SiH₂—R², and R¹—SiH₂—SiHR²—SiH₃, wherein R¹ and R² are independently selected from NH₂, NHR⁹, and NR⁹R¹⁰, and R⁹ and R¹⁰ are independently selected from H and a C₁ to C₄ alkyl.

In some embodiments, at least one of R³ and R⁴ is a C₁ to C₄ alkyl.

In some embodiments, the silicon precursor comprises a silylamine.

In some embodiments, the silicon precursor comprises a compound that can be represented by a chemical structure according to formula (1)

wherein R₁₁ and R₁₂ are independently selected from H and a C₁ to C₄ alkyl.

In some embodiments, the silicon precursor comprises a cyclosiloxane comprising at least one amine group.

In some embodiments, the cyclosiloxane further comprises one or more C₁ to C₄ alkyl substituents.

In some embodiments, the amine group is selected from NH₂, NHR¹³, and NR¹³R¹⁴, with R¹³ and R¹⁴ independently selected from H and a C₁ to C₄ alkyl.

In some embodiments, the plasma pre-treatment comprises subjecting the substrate to a noble gas plasma.

In some embodiments, the plasma pre-treatment comprises subjecting the substrate to a nitrogen-containing plasma.

In some embodiments, the plasma pre-treatment comprises subjecting the substrate to a first plasma treatment and subjecting the substrate to a second plasma treatment.

In some embodiments, the first plasma treatment comprises generating a nitrogen-containing plasma in the reaction chamber.

In some embodiments, the nitrogen-containing plasma is a N₂-containing plasma.

In some embodiments, the second plasma treatment comprises generating a noble gas-containing plasma in the reaction chamber.

In some embodiments, the noble gas-containing plasma is an argon-containing plasma.

In some embodiments, the substrate is maintained at a temperature of at least 100° C. to at most 500° C.

In some embodiments, the reaction chamber is maintained at a pressure of at least 1 Torr to at most 20 Torr.

In some embodiments, the method comprises executing a plurality of super cycles. A super cycle comprises the step of subjecting the substrate to a plasma pre-treatment; and, the step of selectively depositing a silicon-containing material on the lower surface.

In some embodiments, the post silicon precursor pulse plasma treatment comprises generating an oxygen-containing plasma in the reaction chamber, and the silicon-containing material comprises silicon oxide.

In some embodiments, the oxygen-containing plasma is an O₂-containing plasma.

In some embodiments, the step of selectively depositing a material on the lower surface is done at a growth rate of at least 0.1 Å per sub cycle to at most 10 Å per sub cycle.

Further described herein is a semiconductor processing apparatus. It comprises a reaction chamber which in turn comprises a substrate support for supporting a substrate. The substrate comprises one or more gap features. The semiconductor processing apparatus further comprises a heater constructed and arranged to heat the substrate in the reaction chamber. The semiconductor processing apparatus further comprises a first plasma gas source in fluid communication with the reaction chamber via a first plasma gas valve. The semiconductor processing apparatus further comprises a second plasma gas source in fluid connection with the reaction chamber via a second plasma gas valve. The semiconductor processing apparatus further comprises a third plasma gas source in fluid connection with the reaction chamber via a third plasma gas valve. The semiconductor processing apparatus further comprises a plasma module comprising a radio frequency power source constructed and arranged to generate a plasma in the reaction chamber. The semiconductor processing apparatus further comprises one or more silicon precursor sources in fluid connection with the reaction chamber via one or more precursor valves. The semiconductor processing apparatus further comprises a controller configured for causing the apparatus to perform a method as described herein.

These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of certain embodiments having reference to the attached figures. The invention is not being limited to any particular embodiments disclosed.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

A more complete understanding of the embodiments of the present disclosure may be derived by referring to the detailed description and claims when considered in connection with the following illustrative figures.

FIG. 1 is a schematic representation of a plasma-enhanced atomic layer deposition (PEALD) apparatus suitable for depositing a structure and/or for performing a method in accordance with at least one embodiment of the present disclosure.

FIG. 2 shows a schematic representation of a substrate (200) comprising a gap feature (210).

FIG. 3 shows a schematic representation of an embodiment of a method as described herein.

FIG. 4 shows a schematic representation of an embodiment of a method as described herein.

FIG. 5 shows a schematic representation of an embodiment of a part of a method for selectively depositing a silicon-containing material on the lower surface of a gap feature comprised in a substrate.

FIG. 6 shows a transmission electron microscopy (TEM) micrograph of silicon oxide deposited in a gap feature by means of an embodiment of a method as described herein.

FIG. 7 shows selected components of an embodiment of a plasma-enhanced atomic layer deposition (PEALD) apparatus.

Throughout the figures, the following numbering is adhered to: 1—substrate; 2—lower stage/conductive flat-plate electrode; 3—reaction chamber; 4—upper electrode/conductive flat-plate electrode; 5—transfer chamber; 6—exhaust line; 11—interior of a reaction chamber; 12—electrically grounded side; 13—circular duct; 14—separation plate; 16—interior of the transfer chamber; 7—exhaust line; 21—gas line; 22—gas line; 24—gas seal line; 25—power source; 200—substrate; 210—gap feature; 211—upper part; 212—lower part; 311—step of positioning a substrate on a substrate support; 312—step of subjecting the substrate to a plasma treatment; 315—post-plasma purge; 316—step of depositing a material on a lower surface; 317—post-deposition purge; 318—method end; 319—repeat; 411—step of positioning a substrate on a substrate support; 412—step of subjecting the substrate to a first plasma treatment; 413—inter-plasma purge; 414—step of subjecting the substrate to a first plasma treatment; 415—post-plasma purge; 416—step of depositing a silicon-containing material on a lower surface; 417—post-deposition purge; 418—method end; 419—repeat; 511—method start; 512—expose a substrate to a silicon precursor; 513—purge; 514—step of exposing the substrate to a post-precursor exposure plasma treatment; 515—purge; 516—method end; 517—repeat.

It will be appreciated that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of illustrated embodiments of the present disclosure.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The description of exemplary embodiments of methods, structures, devices and systems provided below is merely exemplary and is intended for purposes of illustration only; the following description is not intended to limit the scope of the disclosure or the claims. Moreover, recitation of multiple embodiments having stated features is not intended to exclude other embodiments having additional features or other embodiments incorporating different combinations of the stated features. For example, various embodiments are set forth as exemplary embodiments and may be recited in the dependent claims. Unless otherwise noted, the exemplary embodiments or components thereof may be combined or may be applied separate from each other.

In this disclosure, “gas” can include material that is a gas at normal temperature and pressure (NTP), a vaporized solid and/or a vaporized liquid, and can be constituted by a single gas or a mixture of gases, depending on the context. A gas other than the process gas, i.e., a gas introduced without passing through a gas distribution assembly, a multi-port injection system, other gas distribution device, or the like, can be used for, e.g., sealing the reaction space, and can include a seal gas, such as a rare gas. The terms “rare gas” and “noble gas” as used herein may be used interchangeably. In some cases, the term “precursor” can refer to a compound that participates in the chemical reaction that produces another compound, and particularly to a compound that constitutes a film matrix or a main skeleton of a film, or that is incorporated in a film as a constituent part thereof; the term “reactant” may be used interchangeably with the term precursor.

As used herein, the term “substrate” can refer to any underlying material or materials that can be used to form, or upon which, a device, a circuit, or a film can be formed. A substrate can include a bulk material, such as silicon (e.g., single-crystal silicon), other Group IV materials, such as germanium, or other semiconductor materials, such as a Group II-VI or Group III-V semiconductor, and can include one or more layers overlying or underlying the bulk material.

Further, in this disclosure, any two numbers of a variable can constitute a workable range of the variable, and any ranges indicated may include or exclude the endpoints. Additionally, any values of variables indicated (regardless of whether they are indicated with “about” or not) may refer to precise values or approximate values and include equivalents, and may refer to average, median, representative, majority, or the like. Further, in this disclosure, the terms “including,” “constituted by” and “having” refer independently to “typically or broadly comprising,” “comprising,” “consisting essentially of,” or “consisting of” in some embodiments. In this disclosure, any defined meanings do not necessarily exclude ordinary and customary meanings in some embodiments.

As used herein, the term “comprising” indicates that certain features are included, but that it does not exclude the presence of other features, as long as they do not render the claim or embodiment unworkable. In some embodiments, the term “comprising” includes “consisting”. As used herein, the term “consisting” indicates that no further features are present in the apparatus/method/product apart from the ones following said wording. When the term “consisting” is used referring to a chemical compound, it indicates that the chemical compound only contains the components which are listed.

As used herein, the term “purge” refers to a process step in which precursor and/or reactive species are removed from a reaction chamber. During a purge, an inert or substantially inert gas can be provided to the reaction chamber. Additionally or alternatively, the reaction chamber may be evacuated during a purge.

Described herein is a method for filling a gap feature. The gap feature is comprised in a substrate, and can be located at or near the substrate's surface. Optionally, the substrate can comprise multiple gap features, e.g. a plurality of gap features. A gap feature comprises an upper part comprising an upper surface and a lower part comprising a lower surface. Suitable substrates include semiconductor wafers, e.g. silicon wafers. The present methods can be used during the manufacture of various semiconductor devices and are particularly useful for filling gap features having a high aspect ratio and a particularly small width, e.g. having a width smaller than 10 nm and an aspect ratio higher than 2, or 5, or 10, or 20. The method comprises a step of positioning the substrate on a substrate support in a reaction chamber. The method further comprises a step of subjecting the substrate to a plasma pre-treatment. The plasma pre-treatment results in an inhibition of the upper surface while the lower surface is left substantially unaffected. After the plasma pre-treatment, the method further comprises a step of selectively depositing a silicon-containing material on the lower surface. Optionally, a purge precedes the step of selectively depositing the material on the lower surface. It shall be understood that no plasma is generated in the reaction chamber during the purge. Also, it shall be understood that the step of selectively depositing a silicon-containing material on the lower surface comprises a cyclical process comprising sub-steps that may be continually repeated until a desired thickness of silicon-containing material has been deposited on the lower surface. Exemplary silicon-containing materials include silicon oxide and silicon oxycarbide. The cyclical process comprises a plurality of cycles, also called sub cycles. A sub cycle comprises, in the following order: a step of exposing the substrate to a silicon precursor in a silicon precursor pulse, and a step of exposing the substrate to a post silicon precursor pulse plasma treatment. Optionally, step of exposing the substrate to the silicon precursor is preceded by a purge. Optionally, step of exposing the substrate to the silicon precursor is followed by a purge. It shall be understood that no plasma is generated in the reaction chamber during the purges. The step of exposing the substrate to a silicon precursor results in chemisorption of the silicon precursor on the lower surface. In other words, by exposing the substrate to the silicon precursor, more silicon precursor is chemisorbed on the unpassivated lower surface compared to the plasma-passivated upper surface. The step of exposing the substrate to a post silicon precursor pulse plasma treatment results in a reaction between one or more reactive species comprised in the plasma to react with the silicon precursor that chemisorbed on the lower surface during the step of exposing the substrate to a silicon precursor. In some embodiments, the method comprises entirely filling the gap feature with the silicon-containing material. This can be done, for example, by repeating the cyclical process until the entire gap feature is filled with the silicon-containing material.

Advantageously, such methods offer a very short cycle time. Indeed, the deposition time needed for obtaining a specific film thickness can be shortened by 50% or more, so higher throughput and less process-induced damage to underlying layers can result. An example of process-induced damage is plasma-induced damage.

In some embodiments, the cyclical process comprises from at least 2 sub cycles to at most 20000 sub cycles. For example, a cyclical deposition process can comprise 2 sub cycles, 3 sub cycles, 5 sub cycles, 10 sub cycles, 20 sub cycles, 30 sub cycles, 60 sub cycles, 100 sub cycles, 200 sub cycles, 500 sub cycles, 1000 sub cycles, 2000 sub cycles, 5000 sub cycles, 10000 sub cycles, or more.

In some embodiments, the post silicon precursor pulse plasma treatment comprises generating an oxygen-containing plasma in the reaction chamber, and the silicon-containing material comprises silicon oxide. In some embodiments, the oxygen-containing plasma is an O₂-containing plasma. Accordingly, the methods as disclosed herein can be used for various applications, for example for filling a gap feature with seam-free SiO₂ for the purpose of shallow trench insulation. Such seam-free shallow trench insulation can advantageously reduce leakage currents, etch resistance, and improve resilience with respect to chemical mechanical polishing processes. In addition, such SiO₂ films can have a very low carbon content. In addition, such SiO₂ films can have a very low nitrogen content.

In some embodiments, the post silicon precursor pulse plasma treatment comprises exposing the substrate to an oxygen plasma, and O₂ is used as a plasma gas. In some embodiments, O₂ is provided to the reaction chamber at a flow rate of a least 100 sccm to at most 10 000 sccm, or at a flow rate of at least 200 sccm to at most 5000 sccm, or at a flow rate of at least 500 sccm to at most 1000 sccm. In some embodiments, the oxygen plasma is generated by means of an RF generator operating at a plasma power of at least 50 W to at most 200 W. In some embodiments, the oxygen plasma is, during an oxygen plasma pulse, generated for at least 0.1 s to at most 10 s, or for at least 0.2 s to at most 5 s, or for at least 0.5 s to at most 2 s. In some embodiments, exposing the substrate to an oxygen plasma is followed by a purge, the purge lasting from at least 0.2 s to at most 10 s, or from at least 1 s to at most 5 s. It shall be understood that no plasma is generated in the reaction chamber during the purge.

In some embodiments, the step of selectively depositing a material on the lower surface is done at a growth rate of at least 0.1 Å/cycle to at most 10 Å/cycle, for example a growth rate of from at least 0.2 Å/cycle to at most 3 Å/cycle, or from at least 0.3 to at most 1 Å/cycle. For example, the material is deposited on the lower surface at a growth rate of 0.49 Å/cycle. In some embodiments, the growth rate on the upper surface is from at least 2 to at most 20 times slower on the upper surface. In some embodiments, the growth rate on the upper surface is from at least 2 to at most 5 times slower on the upper surface. In some embodiments, the growth rate on the upper surface is from at least 5 to at most 10 times slower on the upper surface. In some embodiments, the growth rate on the upper surface is from at least 10 to at most 20 times slower on the upper surface. In some embodiments, the growth rate on the upper surface is less than 0.1 Å/cycle. In some embodiments, the growth rate on the upper surface is 0 Å/cycle.

It was surprisingly found that using specific silicon precursors, a high growth rate and bottom-up growth can be obtained. Thus, in some embodiments, the silicon precursor comprises an amine group and two or more silicon atoms.

In some embodiments, the silicon precursor comprises a compound selected from the list consisting of an aminosilane, a silylamine, and a cyclosiloxane. Exemplary silicon precursors and their methods of preparation are disclosed, for example, in WO2015048237A2, WO2015047914A1, U.S. Ser. No. 10/192,734B2.

In some embodiments, the amine group is selected from NH₂, NHR^(i), and NR^(i)R^(ii). In some embodiments, R^(i) and R^(ii) are hydrocarbyls. In some embodiments, R^(i) and R^(ii) are identical. In some embodiments, R^(i) and R^(ii) are different. In some embodiments, R^(i) and R^(ii) independently selected from a C₁ to C₄ alkyl or alkenyl. In some embodiments, at least one of R^(i) and R^(ii) is a C₁ to C₄ alkyl.

In some embodiments, the silicon precursor comprises an alkylaminosilane. In some embodiments, the silicon precursor is a disilane or trisilane comprising one or more amine groups.

In some embodiments, the silicon precursor is selected from SiR¹R³R⁴—SiR²R⁵R⁶, SiR¹R³R⁴—SiR⁵R⁶—SiR²R⁷R⁸, and SiR¹R³R⁴—SiR²R⁵—SiR⁶R⁷R⁸. It shall be understood that R¹ and R² are NR⁹R¹⁰, with R³, R⁴, R⁵, R⁶, R⁷, R⁸, R⁹, and R¹⁰ independently being selected from H and hydrocarbyl. In some embodiments, R³, R⁴, R⁵, R⁶, R⁷, R⁸, R⁹, and R¹⁰ are independently selected from H, C₁ to C₄ alkyl, C₁ to C₄ alkenyl, and C₄ to C₈ aryl. In some embodiments, R³, R⁴, R⁵, R⁶, R⁷, R⁸, R⁹, and R¹⁰ are independently selected from H and a C₁ to C₄ alkyl. In some embodiments, at least one of R³, R⁴, R⁵, R⁶, R⁷, R⁸, R⁹, and R¹⁰ is H. In some embodiments, at least one of R³, R⁴, R⁵, R⁶, R⁷, R⁸, R⁹, and R¹⁰ is methyl. In some embodiments, at least one of R³, R⁴, R⁵, R⁶, R⁷, R⁸, R⁹, and R¹⁰ is ethyl. In some embodiments, at least one of R³, R⁴, R⁵, R⁶, R⁷, R⁸, R⁹, and R¹⁰ is propyl. In some embodiments, at least one of R³, R⁴, R⁵, R⁶, R⁷, R⁸, R⁹, and R¹⁰ is isopropyl. In some embodiments, all of R³, R⁴, R⁵, R⁶, R⁷, R⁸, R⁹, and R¹⁰ are methyl. In some embodiments, the silicon precursor comprises dimethylaminopentamethyldisilane.

In some embodiments, the silicon precursor is selected from R¹—SiH₂—SiH₃, R¹—SiH₂—SiH₂—SiH₂—R², and R¹—SiH₂—SiHR²—SiH₃, in which R¹ and R² are independently selected from NH₂, NHR⁹, and NR⁹R¹⁰, and in which R⁹ and R¹⁰ being independently selected from H and a C₁ to C₄ hydrocarbyl. In some embodiments, R⁹ and R¹⁰ are independently selected from H, C₁ to C₄ alkyl, C₁ to C₄ alkenyl, and C₄ to C₈ aryl. In some embodiments, R⁹ and R¹⁰ are independently selected from H and a C₁ to C₄ alkyl. In some embodiments, at least one of R⁹ and R¹⁰ is H. In some embodiments, least one of R⁹ and R¹⁰ is methyl. In some embodiments, least one of R⁹ and R¹⁰ is ethyl. In some embodiments, least one of R⁹ and R¹⁰ is propyl. In some embodiments, least one of R⁹ and R¹⁰ is isopropyl. In some embodiments, R⁹ and R¹⁰ are methyl. In some embodiments, at least one of R³ and R⁴ is a C₁ to C₄ alkyl. In some embodiments, the silicon precursor comprises an alkylaminosilane selected from diisopropylaminodisilane, and disec-butylaminodisilane.

In some embodiments, the silicon precursor comprises a silylamine.

In some embodiments, the silicon precursor can be represented by a chemical formula according to formula (i)

wherein R¹¹ and R¹² are independently selected from H and a C₁ to C₄ alkyl. In some embodiments, at least one of R¹¹ and R¹² is H. In some embodiments, at least one of R¹¹ and R¹² is methyl. In some embodiments, at least one of R¹¹ and R¹² is ethyl. In some embodiments, at least one of R¹¹ and R¹² is propyl. In some embodiments, at least one of R¹¹ and R¹² is butyl. In some embodiments, at least one of R¹¹ and R¹² is isopropyl. In some embodiments, R¹¹ and R¹² are isopropyl.

In some embodiments, the silicon precursor comprises a cyclosiloxane that comprises at least one amine group. In some embodiments, the amine group is selected from NH₂, NHR^(i), and NR^(i)R^(ii). In some embodiments, R^(i) and R^(ii) are hydrocarbyls. In some embodiments, R^(i) and R^(ii) are identical. In some embodiments, R^(i) and R^(ii) are different. In some embodiments, R^(i) and R^(ii) independently selected from a C₁ to C₄ alkyl or alkenyl. In some embodiments, at least one of R^(i) and R^(ii) is a C₁ to C₄ alkyl. In some embodiments, the amine group is selected from NH₂, NHR¹³, and NR¹³R¹⁴, with R¹³ and R¹⁴ being independently selected from H and a C₁ to C₄ alkyl.

In some embodiments, the cyclosiloxane further comprises one or more C₁ to C₄ alkyl substituents. In some embodiments, at least one of the C₁ to C₄ alkyl substituents is methyl. In some embodiments, at least one of the C₁ to C₄ alkyl substituents is ethyl. In some embodiments, at least one of the C₁ to C₄ alkyl substituents is propyl. In some embodiments, at least one of the C₁ to C₄ alkyl substituents is butyl. One suitable siloxane includes 2-diethylamino-2,4,6,8-tetramethylcyclotetrasiloxane.

It shall be understood that the application of the plasma pre-treatment results in an inhibition of the upper surface whereas the lower surface is left substantially unaffected, or at least less affected than the upper surface. In other words, the upper surface can be suitably rendered less reactive towards a silicon precursor that can be subsequently provided to the reaction chamber. Stated differently still, subjecting the substrate to the plasma pre-treatment can result in an inhibition gradient in the gap feature. In particular, the inhibition is stronger in the upper part of the gap than in the lower part of the gap. In other words, the inhibition gradually decreases going from the upper part of the gap to the lower part of the gap. Without the invention being bound to any particular theory or mode of operation, it is believed that the inhibition at the upper surface is caused by depletion of reactive surface groups such as hydroxyl and amine groups near the top of the surface, whereas reactive surface groups near the lower surface, i.e. near the bottom of the trench, are believed to be less, or not, affected by the plasma pre-treatment.

A plasma pre-treatment employing no more than one plasma advantageously results in a short cycle time. In addition, when that plasma is kept on for only a short time, e.g. for a time of at least 5 seconds to at most 15 seconds, dielectric layers such as SiO₂ having advantageous properties such as low leakage, high breakdown voltage can be obtained. When the dielectric layer is deposited on, or near, a channel region in a transistor, e.g. a silicon transistor or a thin-film transistor, a high electron mobility in that transistor's channel can be advantageously obtained.

In some embodiments, the plasma pre-treatment results in a passivation gradient, i.e. a gradual change of passivation intensity, from the upper surface towards the lower surface. In such a case, the step of exposing the substrate to a precursor can result in a gradual change in the density of chemisorbed precursor per unit area from the lower surface to the upper surface. The post silicon precursor pulse plasma treatment then allows one or more reactive species comprised in the plasma to react with the chemisorbed precursor to form a material. Since more precursor is chemisorbed on the lower surface compared to the upper surface, more material is formed on the lower surface compared to the upper surface. In other words, the material is selectively grown in a bottom-up way.

In some embodiments, the plasma pre-treatment comprises subjecting the substrate to a noble gas plasma. In some embodiments, the noble gas plasma is an argon plasma.

In some embodiments, the plasma pre-treatment comprises subjecting the substrate to a nitrogen-containing plasma. In some embodiments, the nitrogen-containing plasma is an N₂ plasma. In some embodiments, the nitrogen-containing plasma is an NH₃ plasma.

In some embodiments, the plasma-pre-treatment comprises exposing the substrate to a H₂—N₂ plasma. It shall be understood that a H₂—N₂ plasma refers to a plasma that employs a plasma gas that comprises H₂ and N₂. A H₂—N₂ plasma can advantageously be used for filling a gap with a silicon-containing material using an alkylaminosilane such as Bis(diethylamino)silane.

In some embodiments, the plasma pre-treatment comprises subjecting the substrate to a hydrogen-containing plasma. In some embodiments, the hydrogen-containing plasma is a H₂ plasma.

In some embodiments, the plasma pre-treatment comprises subjecting the substrate to a first plasma treatment and subjecting the substrate to a second plasma treatment. It shall be understood that the first and second plasma treatments are different, i.e. not identical. Optionally, the first and second plasma treatments are separated by a purge. It shall be understood that no plasma is generated in the reaction chamber during a purge.

In some embodiments, the first plasma treatment comprises generating a nitrogen-containing plasma in the reaction chamber. In some embodiments, the nitrogen-containing plasma is a N₂-containing plasma. In other words, in some embodiments, a plasma gas comprising N₂ is used for generating the nitrogen-containing plasma.

In some embodiments, the second plasma treatment comprises generating a noble gas-containing plasma in the reaction chamber. In some embodiments, the noble gas-containing plasma is an argon-containing plasma.

In some embodiments, the first plasma treatment comprises generating a nitrogen plasma in the reaction chamber, and the second plasma treatment comprises generating a noble gas plasma in the reaction chamber. In such embodiments, materials such as silicon oxide shallow trench isolation selectively deposited after the first and second plasma treatments can advantageously feature low to negligible C residues, and high quality films. In addition, when the substrate comprises Si fins, these plasma treatments advantageously limit or avoid oxidation of the silicon fins. Additionally, the use of a noble gas plasma after the nitrogen plasma can advantageously reduce or eliminate the amount of N-containing surface groups, also known as nitrogen residues, on the substrate.

In some embodiments, the first plasma treatment comprises exposing the substrate to a nitrogen plasma, and the plasma gas comprises N₂. In some embodiments, N₂ is provided to the reaction chamber at a flow rate of at least 200 sccm to at most 2000 sccm, or at a flow rate of at least 400 sccm to at most 1200 sccm, or at a flow rate of at least 600 sccm to at most 1000 sccm. In some embodiments, the nitrogen plasma is generated by means of an RF generator at a plasma power of from at least 100 W to at most 1000 W, for example at a plasma power of at least 200 W to at most 500 W. In some embodiments, the N₂ plasma is generated for a duration of at least 5 s to at most 50 s, for example for a duration of at least 10 s to at most 20 s. In some embodiments, the N₂ plasma is generated for a duration of at least 0.01 s to at most 50 s, for example for a duration of at least 0.2 s to at most 20 s, for example for a duration of at least 0.5 s to at most 10 s, for example for a duration of at least 1 s to at most 5 s. In some embodiments, the N₂ plasma is followed by a purge that lasts from at least 1 s to at most 5 s. In some embodiments, the N₂ plasma is followed by a purge that lasts from at least 0.1 s to at most 10 s. It shall be understood that no plasma is generated in the reaction chamber during the purge. Also, it shall be understood that purge time of at least 1 s can be particularly advantageous when the plasma gas is changed from one process step to the other, as can be the case when the substrate is first subjected to a first plasma treatment, and then to a second plasma treatment.

In some embodiments, the second plasma treatment comprises exposing the substrate to an argon plasma, and the plasma gas comprises Ar. In some embodiments, Ar is provided to the reaction chamber at a flow rate of at least 1 slm to at most 10 slm, or at a flow rate of at least 2 slm to at most 5 slm. In some embodiments, the argon plasma is generated by means of an RF generator at a plasma power of from at least 100 W to at most 1000 W, for example at a plasma power of at least 200 W to at most 500 W. In some embodiments, the argon plasma is generated for a duration of at least 5 s to at most 50 s, for example for a duration of at least 10 s to at most 20 s. In some embodiments, the argon plasma is followed by a purge that lasts from at least 0.1 s to at most 2 s, for example from at least 0.2 s to at most 1 s. It shall be understood that no plasma is generated in the reaction chamber during the purge. Note that the above values were given for when a 300 mm wafer is used as a substrate, and that the values can be readily adapted to different substrate sizes, if desired.

In some embodiments, the substrate is maintained at a temperature of at least 100° C. to at most 500° C., or at a temperature of at least 100° C. to at most 200° C., or at a temperature of at least 200° C. to at most 300° C., or at a temperature of at least 300° C. to at most 400° C., or at a temperature of at least 400° C. to at most 500° C.

In some embodiments, the reaction chamber is maintained at a pressure of at least 0.1 Torr to at most 200 Torr, or of at least 0.2 Torr to at most 100 Torr, or of at least 0.5 Torr to at most 50 Torr, or of at least 1 Torr to at most 20 Torr, or of at least 2 Torr to at most 10 Torr, e.g. the reaction chamber can be maintained at a pressure of 5 Torr.

In some embodiments, the silicon precursor pulses have a duration of at least 1 s to at most 20 s, or of at least 2 s to at most 10 s, or of at least 3 s to at most 5 s. In some embodiments, the silicon precursor pulses have a duration of at least 0.1 s to at most 20 s, or of at least 0.2 s to at most 10 s, or of at least 0.5 s to at most 5 s, or of at least 1 s to at most 2 s. In some embodiments, the silicon precursor pulses are followed by purges, the purges having a duration of at least 0.2 s to at most 20 s, or of at least 0.5 s to at most 10 s, or of at least 1 s to at most 5 s. It shall be understood that no plasma is generated in the reaction chamber during the purge.

In some embodiments, the method comprises consecutively executing a plurality of super cycles. A super cycle comprises the step of subjecting the substrate to a plasma pre-treatment; and, the step of selectively depositing a silicon-containing material on the lower surface. In some embodiments, the method comprises executing the super cycle for at least 5 times to at most 10 000 times, or from at least 10 times to at most 5 000 times, or from at least 20 times to at most 2 000 times, or from at least 50 times to at most 1000 times, or from at least 100 times to at most 500 times. In some embodiments, the method comprises executing the super cycle from at least 5 times to at most 50 times, or from at least 10 times to at most 20 times. In some embodiments, consecutive super cycles are separated from each other by means of a purge. It shall be understood that no plasma is generated in the reaction chamber during the purge.

Further described herein is a semiconductor processing apparatus. The apparatus comprises a reaction chamber, a heater, a first plasma gas source, a second plasma gas source, a plasma module, one or more precursor sources, and a controller. Optionally, the apparatus further comprises a third plasma gas source. The substrate support suitably allows supporting a substrate that comprises one or more gap features. The heater is constructed and arranged to heat the substrate in the reaction chamber. The first plasma gas source is in fluid communication via a first plasma gas valve with the reaction chamber. The first plasma gas source can be arranged, for example, to provide a nitrogen-containing gas and/or a noble gas containing gas to the reaction chamber. The second plasma gas source is in fluid connection with the reaction chamber via a second plasma gas valve. The second plasma gas source can be arranged, for example, to provide an oxygen-containing gas to the reaction chamber. When present, the third plasma gas source can be in fluid connection with the reaction chamber via a third plasma gas valve. The third plasma gas source can be arranged, for example, to provide a nitrogen-containing gas and/or a noble gas containing gas to the reaction chamber. The plasma module comprises a radio frequency power source that is constructed and arranged to generate a plasma in the reaction chamber. The one or more precursor sources are in fluid connection with the reaction chamber via one or more precursor valves. Suitably, the semiconductor processing apparatus can further comprise an exhaust for exhausting reaction products, carrier gas, and unused precursor and co-reactant. The controller comprises a processor and one or more memory modules, and is programmed or otherwise configured for causing the apparatus to perform a method as described herein.

Optionally, the system is configured for providing at least one of the precursors to the reaction chamber by means of a carrier gas. Suitable carrier gasses include noble gasses. In other words, in some embodiments, the semiconductor processing system comprises a gas injection system comprising a precursor delivery system that employs a carrier gas for carrying the precursor to one or more reaction chambers.

The presently provided methods may be executed in any suitable apparatus, including in an embodiment of a semiconductor processing system as shown in FIG. 1. FIG. 1 is a schematic view of a plasma-enhanced atomic layer deposition (PEALD) apparatus, usable in some embodiments of the present invention. In this figure, by providing a pair of electrically conductive flat-plate electrodes (2,4) in parallel and facing each other in the interior (11) (reaction zone) of a reaction chamber (3), applying RF power (e.g. at 13.56 MHz and/or 27 MHz) from a power source (25) to one side, and electrically grounding the other side (12), a plasma can be generated between the electrodes. Of course, there is no need for the semiconductor processing apparatus to generate a plasma during the steps when a precursor is provided to the reaction chamber, or during purges between subsequent processing steps, and no RF power need be applied to any one of the electrodes during those steps or purges. A temperature regulator may be provided in a lower stage (2), i.e. the lower electrode. A substrate (1) is placed thereon and its temperature is kept constant at a given temperature. The upper electrode (4) can serve as a shower plate as well, and various gasses such as a plasma gas, a reactant gas and/or a dilution gas, if any, as well as a precursor gas can be introduced into the reaction chamber (3) through a gas line (21) and a gas line (22), respectively, and through the shower plate (4). Additionally, in the reaction chamber (3), a circular duct (13) with an exhaust line (7) is provided, through which the gas in the interior (11) of the reaction chamber (3) is exhausted. Additionally, a transfer chamber (5) is disposed below the reaction chamber (3) and is provided with a gas seal line (24) to introduce seal gas into the interior (11) of the reaction chamber (3) via the interior (16) of the transfer chamber (5) wherein a separation plate (14) for separating the reaction zone and the transfer zone is provided.

Note that a gate valve through which a wafer may be transferred into or from the transfer chamber (5) is omitted from this figure. The transfer chamber is also provided with an exhaust line (6). In some embodiments, the deposition of the silicon oxide and the surface treatment are performed in the same reaction space, so that all the steps can continuously be conducted without any need for intermediate steps of evacuating reaction chambers, pumping down reaction chambers, or exposing the substrate to atmospheric air.

FIG. 2 shows a schematic representation of a substrate (200) comprising a gap feature (210). The gap feature (210) comprises an upper part (211) and a lower part (212). The upper part (211) comprises an upper surface, and the lower part (212) comprises a lower surface. By subjecting the substrate (200) to a first plasma treatment and a second plasma treatment, the upper surface can be substantially inhibited. In other words, the first and second plasma treatments can suitably render the upper surface relatively unreactive towards a precursor compared to the lower surface.

FIG. 3 shows a schematic representation of an embodiment of a method as described herein. The method comprises a step (311) of positioning a substrate on a substrate support. The substrate comprises a gap feature. The substrate is then subjected to a plasma treatment (312) as described herein. Optionally, the reaction chamber is then purged using a post-plasma purge (315). Purging can be done, for example, by means of a substantially inert gas such as a noble gas. Exemplary noble gasses include He, Ne, Ar, Xe, and Kr. The method further comprises a step (316) of depositing a silicon-containing material on the lower surface of the gap feature, by means of a technique as described herein. Optionally, the reaction chamber is then purged using a post-deposition purge (317). It shall be understood that no plasma is generated in the reaction chamber during the purges. The steps from subjecting the substrate to a plasma treatment (312) to the step of depositing a silicon-containing material on the lower surface of the gap feature (316) can optionally be repeated (319) one or more times, thereby resulting in a plurality of super-cycles comprising subsequent plasma treatments followed by a deposition step. Optionally, subsequent super-cycles are separated by a purge. Thus, a silicon-containing material is deposited in the gap feature. When a desired amount of material has been deposited in the gap, the method ends (318).

FIG. 4 shows a schematic representation of an embodiment of a method as described herein. The method comprises a step (411) of positioning a substrate on a substrate support. The substrate comprises a gap feature. The substrate is then subjected to a first plasma treatment (412) as described herein. Optionally, the reaction chamber is then purged using an inter-plasma purge (413). Purging can be done, for example, by means of a substantially inert gas such as a noble gas. Exemplary noble gasses include He, Ne, Ar, Xe, and Kr. The method further comprises a step (414) of subjecting the substrate to a second plasma treatment as described herein. Optionally, the reaction chamber is then purged using a post-plasma purge (415). The method further comprises a step (416) of depositing a silicon-containing material on the lower surface of the gap feature, by means of a technique as described herein. Optionally, the reaction chamber is then purged using a post-deposition purge (417). It shall be understood that no plasma is generated in the reaction chamber during the purges. The steps from subjecting the substrate to a first plasma treatment (412) to the step of depositing a silicon-containing material on the lower surface of the gap feature can optionally be repeated (419) one or more times, thereby resulting in a plurality of super-cycles comprising subsequent first and second plasma treatments followed by a deposition step. Thus, a silicon-containing material is deposited in the gap feature. When a desired amount of silicon-containing material has been deposited in the gap, the method ends (418).

FIG. 5 shows a schematic representation of an embodiment of a part of a method for selectively depositing a silicon-containing material on the lower surface of a gap feature comprised in a substrate. The part of the method shown in FIG. 5 corresponds to the step of depositing a silicon-containing material on a lower surface (316) as shown in FIG. 3, and/or to the step of depositing a silicon-containing material on a lower surface (416) as shown in FIG. 4, and starts (511) after a step of subjecting the substrate to a plasma treatment, or after a step of subjecting the substrate to a first plasma treatment and subjecting the substrate to a second plasma treatment, or optionally after a purge following any such a step. The substrate is exposed to a silicon precursor (512) which chemisorbs on the lower surface, as described herein. Optionally, the reaction chamber is then purged (513). The method then comprises a step of subjecting the substrate to a third plasma treatment (514). Optionally, the reaction chamber is then purged (515). It shall be understood that no plasma is generated in the reaction chamber during the purges. The steps from exposing the substrate to a silicon precursor (512) to the step of subjecting the substrate to a third plasma treatment (514) can optionally be repeated (517) one or more times, thereby resulting in a plurality of sub-cycles. Thus, a silicon-containing material is deposited in the gap feature. When a desired amount of silicon-containing material has been deposited in the gap, the method ends (516).

FIG. 6 shows a transmission electron microscopy (TEM) micrograph of silicon oxide deposited in a gap feature by means of an embodiment of a method as described herein. In particular, a plurality of super-cycles comprising sequential plasma pre-treatments and steps of selectively depositing silicon oxide on the lower surface were used. The plasma pre-treatments comprises a step of exposing the substrate to a nitrogen plasma, and a subsequent step of exposing the substrate to an argon plasma. During the nitrogen plasma, a N₂ flow rate of 800 sccm was used, a plasma power (i.e. radio frequency (RF) power) of 300 W was used, the N₂ plasma was kept on for 8 seconds, and an inter-plasma purge time of 2 seconds was used. During the argon plasma, an Ar flow rate of 3.7 slm was used, a plasma power (RF power) of 500 W was used, the argon plasma was used for 8 seconds, and a post-plasma purge time of 5 seconds was used. Diisorpropylaminotrisilyylamine was used as a silicon precursor. The post silicon precursor pulse plasma treatment comprises exposing the substrate to an O₂ plasma. During the O₂ plasma, an O₂ flow rate of 800 sccm is used, a plasma power (RF power) of 100 W is used. The O₂ plasma is maintained for 1 seconds. After the O₂ plasma is finished, the reaction chamber is purged for 2 seconds. The above-mentioned process is repeated for 100 super cycles. The reaction chamber is maintained at a pressure of 5 Torr, and the substrate is maintained at a temperature of 300° C. Using such a process, a growth per cycle of 2.29 Å/cycle was obtained at the unpassivated lower part of the gap features, and a growth per cycle of 0.93 Å/cycle. Thus, bottom-up growth in the gap feature can be obtained at a surprisingly high growth rate.

In the process of FIG. 6, a plasma pre-treatment, i.e. a plasma inhibition, was used after every sub-cycle comprising a silicon precursor—post silicon precursor pulse plasma treatment. Alternatively, the plasma pre-treatment can be repeated only every few sub-cycles, e.g. every 3 sub-cycles, every 5 sub-cycles, every 10 sub-cycles, every 20 sub-cycles, or every 50 sub-cycles. Such an alternative process flow can advantageously enhance throughput, reduce plasma-induced damage, e.g. Si or Ge oxidation, though this comes at the expense of top-bottom selectivity.

FIG. 7 shows selected components of an embodiment of a plasma-enhanced atomic layer deposition (PEALD) apparatus (700) that may be used for carrying out a method as described herein. The apparatus (700) comprises a gas line (710), a bypass valve (720), a bypass line (730), a reactor (740), and an exhaust line (750). Such an apparatus comprising a bypass valve (720) can suitably increase throughput of a method as described herein. In particular, the bypass valve (720) can be used to allow for continuous gas flow, even when a certain process gas is not needed in the reaction chamber. The use of a bypass valve (720) can thus allow avoiding the use of gas stabilization steps during the processing of multiple wafers and could make switching to a different gas composition for treatment steps easier, thus improving throughput.

Additionally, the bypass valve allows continuous flow of certain gasses, and may therefore reduce particle contamination as pressure pulses trough lines are avoided. Furthermore flows can be started in bypass mode and may therefore prevent initial particle bursts to the chamber at start up (first wafer effects, pre-recipe requirements etc.).

The gas line (710) can be a line carrying any of the gasses described herein, such as a silicon precursor gas line, or a noble gas line, or a nitrogen gas line, or an oxygen gas line. Advantageously, the apparatus (700) comprises multiple gas lines, such as a silicon precursor gas line, or a noble gas line, or a nitrogen gas line, and an oxygen gas line.

Thus, in some embodiments, the silicon precursor is diverted through a silicon precursor bypass duct during the step of subjecting the substrate to a plasma pre-treatment.

Additionally or alternatively, a plasma gas is diverted through a plasma gas bypass duct, during the step of exposing the substrate to a silicon precursor.

In some embodiments, the plasma gas used during the plasma pre-treatment is diverted using a bypass valve during the step of depositing a silicon-containing material.

In some embodiments, the silicon precursor is diverted using a bypass valve during the plasma pre-treatment and during the step of exposing the substrate to a post silicon precursor pulse plasma treatment.

In some embodiments, the plasma gas used during the step of exposing the substrate to a post silicon precursor pulse plasma treatment is diverted using a bypass valve during the step of subjecting the substrate to a plasma pre-treatment and during the step of exposing the substrate to a silicon precursor.

The example embodiments of the disclosure described herein do not limit the scope of the invention, since these embodiments are merely examples of the embodiments of the invention, which is defined by the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of this invention. Indeed, various modifications of the disclosure, in addition to those shown and described herein, such as alternative useful combinations of the elements described, may become apparent to those skilled in the art from the description. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

In the present disclosure, where conditions and/or structures are not specified, the skilled artisan in the art can readily provide such conditions and/or structures in view of the present disclosure, as a matter of routine experimentation. 

What is claimed is:
 1. A method for filling a gap feature on a substrate surface, the method comprising, in the given order: a step of positioning a substrate on a substrate support in a reaction chamber, the substrate comprising one or more gap features, the one or more gap features comprising an upper part comprising an upper surface and a lower part comprising a lower surface; a step of subjecting the substrate to a plasma pre-treatment, thereby inhibiting the upper surface while leaving the lower surface substantially unaffected; and, a step of selectively depositing a silicon-containing material on the lower surface; wherein the step of selectively depositing a silicon-containing material on the lower surface comprises a cyclical process, the cyclical process comprising a plurality of sub cycles, a sub cycle comprising, in the given order: a step of exposing the substrate to a silicon precursor in a silicon precursor pulse, thereby forming chemisorbed silicon precursor on the lower surface; and, a step of exposing the substrate to a post silicon precursor pulse plasma treatment, thereby allowing one or more reactive species comprised in the plasma to react with the chemisorbed silicon precursor on the lower surface; wherein the silicon precursor comprises an amine group and two or more silicon atoms.
 2. The method according to claim 1 wherein the amine group is selected from NH₂, NHR^(i), and NR^(i)R^(ii), with at least one of R^(i) and R^(ii) being a C₁ to C₄ alkyl.
 3. The method according to claim 1 wherein the silicon precursor comprises a compound selected from the list consisting of an aminosilane, a silylamine, and a cyclosiloxane.
 4. The method according to claim 1 wherein the silicon precursor comprises an alkylaminosilane.
 5. The method according to claim 1 wherein the silicon precursor comprises a compound selected from SiR¹R³R⁴—SiR²R⁵R⁶, SiR¹R³R⁴—SiR⁵R⁶—SiR²R⁷R⁸, and SiR¹R³R⁴—SiR²R⁵—SiR⁶R⁷R⁸, wherein R¹ and R² are NR⁹R¹⁰, with R³, R⁴, R⁵, R⁶ R⁷, R⁸ R⁹, and R¹⁰ being independently selected from H and a C₁ to C₄ alkyl6.
 6. The method according to claim 1 wherein the silicon precursor comprises a silylamine.
 7. The method according to claim 6 wherein the silicon precursor comprises a compound that can be represented by a chemical structure according to formula (1)

wherein R₁₁ and R₁₂ are independently selected from H and a C₁ to C₄ alkyl.
 8. The method according to claim 1 wherein the silicon precursor comprises a cyclosiloxane comprising at least one amine group.
 9. The method according to claim 1 wherein the plasma pre-treatment comprises subjecting the substrate to a noble gas plasma.
 10. The method according to claim 1 wherein the plasma pre-treatment comprises subjecting the substrate to a nitrogen-containing plasma.
 11. The method according to claim 1 wherein the plasma pre-treatment comprises subjecting the substrate to a nitrogen and hydrogen-containing plasma.
 12. The method according to claim 1 wherein the plasma pre-treatment comprises subjecting the substrate to a first plasma treatment and subjecting the substrate to a second plasma treatment.
 13. The method according to claim 12 wherein the first plasma treatment comprises generating a nitrogen-containing plasma in the reaction chamber.
 14. The method according to claim 13 wherein the nitrogen-containing plasma is a N₂-containing plasma.
 15. The method according to claim 12 wherein the second plasma treatment comprises generating a noble gas-containing plasma in the reaction chamber.
 16. The method according to claim 1 comprising executing a plurality of super cycles, a super cycle comprising the step of subjecting the substrate to a plasma pre-treatment; and, the step of selectively depositing a silicon-containing material on the lower surface.
 17. The method according to claim 1 wherein the post silicon precursor pulse plasma treatment comprises generating an oxygen-containing plasma in the reaction chamber, and wherein the silicon-containing material comprises silicon oxide.
 18. The method according to claim 1 wherein, during the step of subjecting the substrate to a plasma pre-treatment, the silicon precursor is diverted through a silicon precursor bypass duct.
 19. The method according claim 1 wherein, during the step of exposing the substrate to a silicon precursor, a plasma gas is diverted through a plasma gas bypass duct.
 20. A semiconductor processing apparatus comprising: a reaction chamber comprising a substrate support for supporting a substrate comprising one or more gap features; a heater constructed and arranged to heat the substrate in the reaction chamber; a first plasma gas source in fluid communication with the reaction chamber via a first plasma gas valve; a second plasma gas source in fluid connection with the reaction chamber via a second plasma gas valve; a third plasma gas source in fluid connection with the reaction chamber via a third plasma gas valve; a plasma module comprising a radio frequency power source constructed and arranged to generate a plasma in the reaction chamber; one or more silicon precursor sources in fluid connection with the reaction chamber via one or more precursor valves; and, a controller configured for causing the apparatus to perform a method according to claim
 1. 